Memory Organization and Interrupt Notes | COM SPPU 2024

Introduction to Advanced Hardware Control

In a processor system like the 8086, executing software commands smoothly requires an organized relationship with hardware memory chips, input/output peripherals, and sudden real-time events. For a processor to operate efficiently without performance drops, its architecture must have a structured way to handle system memory maps, exchange data with hardware peripherals, and handle urgent real-time signals known as interrupts.

This article provides detailed, textbook-quality notes covering advanced memory organization, input-output interfacing strategies, software interrupt systems, and the structural engineering behind the 8259 Programmable Interrupt Controller.

Memory Organization

Memory Segmentation

Memory segmentation is a design technique where the total physical memory space of a computer system is split into distinct, logical blocks called segments. Each segment holds specific types of information, such as executable code, variables, or temporary system stack frames.

The 8086 microprocessor has a 20-bit address bus that allows it to access up to 1 Megabyte (1 MB) of physical memory. However, its internal data processing registers are only 16 bits wide. To bridge this gap, the 1 MB memory space is divided into logical segments. Each segment can be up to 64 Kilobytes (64 KB) in size.

00000H +-----------------------+
       |   Reserved Interrupt  |
       |      Vectors (IVT)    |
00400H +-----------------------+
       |                       |
       |  Code Segment (CS)    | --> Stores program instructions
       |  Up to 64 KB max      |
       +-----------------------+
       |                       |
       |  Data Segment (DS)    | --> Stores program variables
       |  Up to 64 KB max      |
       +-----------------------+
       |                       |
       |  Stack Segment (SS)   | --> Stores return addresses
       |  Up to 64 KB max      |
       +-----------------------+
       |                       |
       |  Extra Segment (ES)   | --> Extra string storage
       |  Up to 64 KB max      |
       +-----------------------+
FFFFFH +-----------------------+

Key Types of Memory Segments

Code Segment (CS): Contains the actual machine code instructions that the processor fetches and executes.
Data Segment (DS): Holds the static variables, global arrays, and constants defined by your software program.
Stack Segment (SS): Allocates memory space to store subroutine return addresses, parameters, and local variables.
Extra Segment (ES): An auxiliary data segment primarily utilized by string instructions to transfer large blocks of information across memory regions.

Advantages of Memory Segmentation

Expanded Memory Reach: Allows 16-bit registers to access a 20-bit, 1 MB address space.
Code Relocation: Programs can easily be placed in different parts of physical memory simply by changing the base segment value.
Data Protection: Separating data, code, and stacks reduces the risk of errors, such as program code accidentally overwriting stack instructions.

Logical to Physical Address Translation

The processor uses a two-part address layout to locate data within software loops:

Logical Address: Composed of a 16-bit Segment Address (base starting point) and a 16-bit Offset Address (distance from the start). It is represented as Segment:Offset.
Physical Address: The final 20-bit wire signal sent across the system bus to find a specific byte on a hardware memory chip.

To calculate the 20-bit physical address, the Bus Interface Unit shifts the 16-bit segment value left by 4 binary bits (multiplying it by 16 in decimal, or adding a hexadecimal zero 0H to its end). It then adds the 16-bit offset address to this value.

Physical Address = (Segment Address × 16) + Offset Address

Step-by-Step Translation Example

Suppose a system needs to fetch an instruction where the Code Segment (CS) contains 3000H and the Instruction Pointer (IP) contains 2500H.

Step 1: Take the Segment Address (3000H) and shift it left by 4 bits (add a hex zero): 30000H.
Step 2: Add the Offset Address (2500H) directly to that value.

  Shifted Segment Value:  3 0 0 0 0 H
+ Offset Value (IP):      0 2 5 0 0 H
-------------------------------------
= Physical Address:       3 2 5 0 0 H

The physical address sent across the system bus is 32500H.

Hinglish Explanation: Memory Segmentation ka matlab hota hai pure 1 MB space ko 64 KB ke chhote chhote logical blocks ya hisso mein baantna. Kyunki 8086 ke registers 16-bit ke hain aur memory lines 20-bit ki, isliye direct access nahi ho sakta. Address nikalne ke liye Segment address ke pichhe ek 0 lagaya jata hai (shift left), aur phir usme Offset value ko add kiya jata hai. Is tarah 16-bit register se 20-bit ka physical address banta hai.

Even and Odd Memory Banks

The 16-bit data bus of the 8086 is split into two 8-bit lines: D0 to D7 (Lower Byte) and D8 to D15 (Upper Byte). To allow the CPU to read or write 8-bit and 16-bit data smoothly, physical memory is split into two parallel 8-bit hardware blocks called Memory Banks.

               +-----------------------------------+
               |       8086 MICROPROCESSOR         |
               +-----------------------------------+
                    | D15-D8            | D7-D0
                    |                   |
           +--------v--------+ +--------v--------+
           | ODD BANK (High) | | EVEN BANK (Low) |
           | Validated by BHE| | Validated by A0 |
           | Address: Odd    | | Address: Even   |
           | (1, 3, 5, 7...) | | (0, 2, 4, 6...) |
           +-----------------+ +-----------------+

1. Even Bank (Lower Bank)

Contains all memory bytes with even physical addresses (00000H, 00002H, 00004H...).
Connected to the lower data lines (D0 to D7).
Activated when address line A0 is Low (0).

2. Odd Bank (Upper Bank)

Contains all memory bytes with odd physical addresses (00001H, 00003H, 00005H...).
Connected to the higher data lines (D8 to D15).
Activated when the Bus High Enable (BHE') control pin is Low (0).

Memory Access Scenarios

The processor uses the A0 and BHE' hardware control pins to read or write different types of data in a single cycle:

BHE' State	A0 State	Selected Bank	Type of Access	Data Bus Used
1 (High)	0 (Low)	Even Bank Only	8-Bit Byte at Even Address	D0 to D7
0 (Low)	1 (High)	Odd Bank Only	8-Bit Byte at Odd Address	D8 to D15
0 (Low)	0 (Low)	Both Banks	16-Bit Word at Aligned Even Address	D0 to D15

Aligned 16-Bit Access: When reading a 16-bit word starting at an even address (e.g., 2000H), both A0 and BHE' go low simultaneously. The processor reads the entire 16-bit word in a single bus cycle.
Misaligned 16-Bit Access: If a program stores a 16-bit word starting at an odd address (e.g., 2001H), the processor requires two separate bus cycles to read the data. In the first cycle, it reads the lower byte from the odd bank. In the second cycle, it reads the upper byte from the next even address in the even bank. This misaligned access slows down program performance.

Read-Write Cycle Timing Diagrams

A timing diagram shows how control signals, address lines, and data streams change over time relative to the system clock. Every memory operation occurs over a sequence of clock states called T-States. A basic memory read or write cycle requires a minimum of four clock states: T1, T2, T3, and T4.

Memory Read Cycle Steps

T1 State: The processor places the 20-bit target address onto the multiplexed address/data lines. The Address Latch Enable (ALE) signal goes high, telling external latch circuits to save the address before the lines change.
T2 State: The processor removes the address from the multiplexed lines to prepare them for data transfer. The Read (RD') control line drops low, signaling the memory chip to prepare its data output.
T3 State: The memory chip puts the requested data onto the data bus lines. The CPU checks the READY pin. If READY is high, the system continues normally. If READY is low (indicating slow memory), the CPU inserts idle Wait States (Tw) to give the memory more time.
T4 State: The processor reads the data from the bus and pulls the RD' signal high, closing the memory access cycle.

Memory Write Cycle Steps

T1 State: The processor outputs the destination address onto the bus lines and pulses ALE high to latch it into memory control circuits.
T2 State: The CPU places the data to be saved onto the data bus lines and drops the Write (WR') control line low.
T3 State: The CPU holds the data steady on the bus lines while the memory chip writes it into storage.
T4 State: The processor pulls the WR' control signal high to secure the data in memory, then clears the data lines for the next cycle.

Address Mapping and Decoding

Address decoding is a technique that ensures only one specific memory chip or peripheral device activates when the processor outputs a particular address.

Because a standard memory chip (e.g., a 64 KB RAM chip) requires fewer address lines than the processor's 20-bit bus, the remaining upper address lines are used to select the chip itself.

Common Decoding Approaches

Absolute (Full) Decoding: Every address line from the CPU is connected to the decoding circuit. Each memory location corresponds to exactly one unique address value, preventing any address overlapping.
Linear (Partial) Decoding: Individual upper address lines are used directly as chip select inputs without decoding logic gates. While this simplifies the hardware design, it creates duplicate addresses for the same memory space (known as memory mirroring or shadowing).

Input/Output (I/O) Interfacing Strategies

Processors must communicate with external peripherals like keyboards, displays, and sensors. There are two primary strategies for mapping these devices into the system's address space.

+-------------------------------------------------------------------+
|                     I/O INTERFACING METHODS                       |
+-------------------------------------------------------------------+
|  MEMORY-MAPPED I/O                 |  I/O-MAPPED I/O (Isolated)   |
|                                    |                              |
|  - Peripherals share memory space  |  - Separate address space    |
|  - Handled like RAM locations       |  - Requires IN/OUT commands  |
|  - Uses standard MOV instructions  |  - Uses dedicated control pins|
+-------------------------------------------------------------------+

Memory-Mapped I/O

In a Memory-Mapped Input-Output design, external peripheral devices are treated exactly like standard locations inside the main memory map.

Working Principle: A block of addresses within the 1 MB memory space is reserved for peripheral devices instead of RAM chips. Sending data to a hardware device uses the same instructions as writing to memory.
Control Signals: Uses the standard memory read and write lines (MEMR' and MEMW').
Instructions Used: Standard data movement commands like MOV, ADD, or AND can manipulate the peripheral port directly.

I/O-Mapped I/O (Isolated I/O)

In an I/O-Mapped Input-Output design, peripheral devices are mapped to an entirely separate, isolated address space independent of main memory.

Working Principle: The 8086 allocates a dedicated 64 KB address space specifically for input/output devices. Peripherals do not consume any of the 1 MB memory space used for software code.
Control Signals: The processor activates the IOR' (I/O Read) and IOW' (I/O Write) control lines, while pulling the M/IO' pin low to indicate a peripheral operation.
Instructions Used: Peripheral data transfers are restricted to two specialized instructions: IN and OUT.

Comparison: Memory-Mapped I/O vs. I/O-Mapped I/O

Architectural Feature	Memory-Mapped I/O	I/O-Mapped I/O
Address Space Assignment	Shared directly within the main memory map.	Kept completely isolated from memory.
Maximum Port Range	Depends on available RAM space (Up to 1 MB).	Limited to 64 KB (65,536 unique ports).
Control Signals Used	`MEMR'` and `MEMW'`.	`IOR'`, `IOW'`, and `M/IO'`.
Instruction Set Access	Any memory command (`MOV`, `AND`, `SUB`).	Only the specialized `IN` and `OUT` commands.
Register Restrictions	Data can move into any internal register.	Data must pass through the `AL` or `AX` accumulator.
Hardware Complexity	Requires larger address decoding circuits.	Simpler decoding logic because port addresses are short.

Interrupt Management

An interrupt is an emergency signal sent to the processor by hardware or software. It temporarily pauses the current program execution flow so the CPU can handle a high-priority task before returning to normal operations.

Core Concepts and Terminology

Interrupt Service Routine (ISR): A specialized block of software code (an execution handler) designed to handle a specific interrupt event. It functions similarly to a subroutine, ending with an IRET (Interrupt Return) instruction.
Interrupt Vector Table (IVT): A dedicated lookup table stored at the very beginning of system memory (00000H to 003FFH). It holds the memory pointer addresses for all the various Interrupt Service Routines.

+----------------------------------------------------+
|   INTERRUPT VECTOR TABLE (IVT) STRUCTURE           |
+----------------------------------------------------+
| Type 255 Pointer (Highest Vector)                  |
| ...                                                |
| Type 1 Pointer: Single-Step Debug Offset & Segment |
| Type 0 Pointer: Divide-by-Zero Offset & Segment     |
+----------------------------------------------------+

The IVT contains 256 entries (numbered Type 0 through Type 255). Each entry is 4 bytes long and contains:

A 2-byte Offset Address for the ISR.
A 2-byte Segment Address for the ISR.

The memory address for any interrupt type is calculated using a simple formula:

IVT Starting Memory Address = Interrupt Type Number × 4

For example, a Type 4 Interrupt pointer is located at physical memory address 00010H ($4 \times 4 = 16$, which is $10$ in hexadecimal).

Hardware vs. Software Interrupts

1. Hardware Interrupts

Hardware interrupts are triggered by external peripheral devices sending electronic signals to the processor's physical input pins.

Non-Maskable Interrupt (NMI): Triggered via the NMI pin (Pin 17). It has a high priority and cannot be ignored or turned off by software. It is reserved for critical system events, such as power failures or hardware memory errors.
Maskable Interrupt (INTR): Triggered via the INTR pin (Pin 18). These interrupts can be ignored or disabled by clearing the Interrupt Flag (IF) to 0 using the CLI command. They are enabled using the STI command.

2. Software Interrupts

Software interrupts are explicitly called from within a program using assembly code instructions. They occur predictably during program execution.

Example: INT 21H calls an operating system service handler, while INT 00H triggers a divide-by-zero safety stop if an operation attempts to divide by zero.

Interrupt Control and Execution Steps

When an interrupt occurs, the processor completes its current instruction and executes a structured sequence to preserve its state:

1.Push Flags to Stack:Context Saving Phase.

The processor copies the 16-bit Flag Register onto the stack to preserve status indicators like the Zero and Carry flags.

2.Clear Control Flags:Disabling Conflicts.

The CPU clears the Interrupt Flag (IF) and Trap Flag (TF) to 0. This disables other maskable interrupts while the current handler runs.

3. Save Return Address:Stack Protection.

The current Code Segment (CS) and Instruction Pointer (IP) addresses are pushed onto the stack so the program can resume later.

4.Fetch ISR Address:Table Lookup.

The CPU uses the interrupt type number to locate the correct 4-byte entry in the Interrupt Vector Table (IVT).

5.Execute ISR Handler:Execution Phase.

The CPU loads the new vector values into CS and IP, jumping directly to the start of the Interrupt Service Routine code block.

6.Return via IRET:Restoration Phase.

When the ISR finishes, the IRET command pops the saved IP, CS, and Flag values back into their registers, resuming the original program.

Hinglish Explanation: Interrupt ek emergency signal hai jo processor ko chalte program se rokkar doosra zaroori kaam karne ko kehta hai. Jab bhi hardware ya software interrupt aata hai, CPU apna chal raha kaam rokne se pehle Flags, CS, aur IP ko Safe Stack mein chupa (push) deta hai. Phir IVT table se address nikal kar ISR (handler code) ko run karta hai. Akhir mein IRET command chalte hi purana data wapas register mein aa jata hai aur normal program chalne lagta hai.

The 8259 Programmable Interrupt Controller (PIC)

The 8086 microprocessor has only one maskable interrupt pin (INTR). In complex computer designs, multiple peripheral devices (such as keyboards, timers, and storage controllers) need to send interrupt requests. The Intel 8259 Programmable Interrupt Controller (PIC) solves this problem by combining up to 8 independent hardware interrupt lines into a single output pin connected to the CPU.

Peripherals (Keyboards, Timers)
  --- IR0 \
  --- IR1  \
  --- IR2   +------------+                  +--------+
  --- IR3   |            |  INT Pin Out     |  8086  |
  --- IR4   |  8259 PIC  |----------------->|  INTR  |
  --- IR5   |            |                  |  Pin   |
  --- IR6  /             |<-----------------|  INTA' |
  --- IR7 /              |  Interrupt Ack   +--------+
            +------------+

Key Features of the 8259 PIC

Manage Multiple Inputs: Handles 8 priority interrupt request lines (IR0 through IR7).
Cascade Expansion: Up to eight 8259 chips can be connected together (cascaded) to manage up to 64 separate hardware interrupt lines.
Programmable Priority: The priority rules can be configured via software (e.g., fixed priority or rotating priority).
Individual Masking: Each of the 8 interrupt lines can be masked (disabled) or unmasked individually.

Internal Block Diagram and Component Description

The internal architecture of the 8259 PIC consists of several interconnected functional blocks that work together to evaluate incoming interrupt requests.

       +--------------------------------------------------------+
       |                  8259 PIC ARCHITECTURE                 |
       +--------------------------------------------------------+
              |                                           |
       +------v------+                             +------v------+
       |     IRR     |                             |  Data Bus   |
       | (Interrupt  |                             |   Buffer    |
       |Request Reg) |                             | (8-Bit Lines|
       +------+------+                             +------+------+
              |                                           |
       +------v------+      +---------------+      +------v------+
       |     PR      |------| Cascade/Buffer|------|  Read/Write |
       | (Priority   |      |   Logic       |      | Control Log |
       |  Resolver)  |      +---------------+      +-------------+
       +------+------+
              |
       +------v------+
       |     ISR     |
       | (In-Service |
       |  Register)  |
       +--------------------------------------------------------+

1. Interrupt Request Register (IRR)

Stores all the interrupt lines (IR0 to IR7) that are currently requesting attention from peripheral devices. It acts as an intake storage register.

2. Priority Resolver (PR)

A hardware logic circuit that evaluates the active requests inside the IRR simultaneously. It determines which request has the highest priority and should be sent to the CPU first.

3. In-Service Register (ISR)

Tracks which interrupt requests have been accepted by the processor and are currently being executed by an Interrupt Service Routine.

4. Interrupt Mask Register (IMR)

An 8-bit register used to disable individual interrupt lines. Setting a bit to 1 masks (disables) its corresponding IR line, causing the 8259 to ignore requests on that line.

5. Control Logic & Data Buffers

Data Bus Buffer: An 8-bit bidirectional channel that allows the CPU to send configuration commands to the 8259 and read its status registers.
Read/Write Control Logic: Accepts input signals from the CPU (such as RD' and WR') to manage data transfers.
Cascade Buffer/Comparator: Manages the communication lines when multiple 8259 chips are linked together in a Master/Slave configuration.

Control and Status Registers

To control the behavior of the 8259 PIC, programmers send configuration commands using two types of command words:

Initialization Command Words (ICWs)

These commands are used to configure the chip's basic hardware setup when the system boots up.

ICW1: Configures the input trigger style (Edge-triggered vs. Level-triggered) and specifies whether the system uses a single 8259 chip or cascaded chips.
ICW2: Defines the base vector address inside the Interrupt Vector Table (IVT) where the IR lines will map.
ICW3: Configures the master/slave relationships if multiple chips are cascaded.
ICW4: Sets the operational mode, such as Special Fully Nested Mode or Automatic End of Interrupt (AEOI) status.

Operational Command Words (OCWs)

These commands are sent during program execution to dynamically alter how interrupts are handled.

OCW1: Directly writes to the Interrupt Mask Register (IMR) to enable or disable specific IR lines.
OCW2: Sends an End of Interrupt (EOI) signal to clear bits in the In-Service Register (ISR) when an interrupt handler finishes, or alters loop priority rules.
OCW3: Configures which internal register (IRR or ISR) will be read during the next status check.

Technical Summary and Revision Points

Logical Memory Structure: Memory segmentation allows 16-bit registers to navigate a 20-bit physical space by shifting segment base registers left by 4 bits and adding an offset address.
Hardware Bank Optimization: Physical memory is divided into Even and Odd 8-bit banks controlled by the A0 and BHE' signals. Aligning data to even memory boundaries maximizes bus efficiency by preventing multi-cycle transfers.
Input-Output Mapping Alternatives: Memory-Mapped I/O treats device registers like standard RAM addresses, offering a wide choice of assembly instructions. Isolated I/O keeps data ports separate from memory, using dedicated control lines and the specialized IN and OUT instructions.
Interrupt Processing Operations: When an interrupt occurs, the processor saves its current state by pushing the flags and return addresses onto the stack. It then looks up the execution address in the Interrupt Vector Table (IVT) and jumps to the Interrupt Service Routine (ISR).
Support Chip Enhancements: The 8259 PIC expands a microprocessor's input capacity by combining up to eight hardware interrupt lines into a single output pin. Internal registers like the IRR, PR, and ISR manage and prioritize these requests automatically.

SEO Keywords

Memory organization and interrupts notes
Logical to physical address translation 8086
Even and odd memory banks BHE A0 functionality
Memory mapped IO vs IO mapped IO differences
Interrupt Vector Table IVT address calculation
Hardware vs software interrupts assembly language
8259 programmable interrupt controller block diagram
Initialization command words ICW 8259 PIC
Interrupt service routine execution steps computer engineering
Read write cycle timing diagram wait states

Unit 4 – Memory Organization and Interrupts